Design Verification Lead

Duty

• – Responsible for Verification from Verification Strategy, Testbench Development, Verification Item List to Simulation, Coverage Analysis
• – Verification Strategy/Test Plan Development: Create Strategy/Plan based on Design specification/Micro Architecture
• – Testbench Development, Simulation/Debugging to identify and resolve any issues/failures of the design
• – Work closely with Synthesis/PD teams to address any defects in Netlist, Timing SDF and ensure specifications are met
• – Coverage analysis to detect uncovered areas that need further testing
• – Documentation and reporting for progress tracking, detailed feedback to design teams,
• verification result
• Requirements:
  • – At least 5+ years of DV engineering experience
  • – Excellent experience in all level Verification (SoC/SS/IP)
  • – Be able to develop Verification Strategy
  • – Good in extracting specifications for Verification Item List
  • – Strong debugging skill especially for complicated designs
  • – Good experience in SDF annotation simulation and related issues